The present invention relates to semiconductor (integrated circuit) memory devices, and more particularly, to semiconductor memory devices having a delay locked loop (DLL) for synchronizing output data to a clock.
A typical DLL locks data output from a semiconductor memory device to an external clock signal. The DLL compares its output signal with the external clock signal, and increases or decreases its delay time to lock the output data to the external clock signal, so that the output timing of the data substantially matches that of the external clock. In order to precisely lock the output data of the memory device to the external clock, it is often necessary to estimate the delay in a data output path and compensate for the delay in a feedback loop of the DLL.
A compensation delay is located in the feedback loop of the DLL to compensate for the delay in the data output path. The compensation delay is typically formed of inverters using a series of resistors and capacitors. In some conventional circuits, the same circuits as those in the data output path are used in the compensation delay, so as to precisely compensate for the delay.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device having a typical DLL 100. Referring to FIG. 1, the typical DLL 100 includes: a clock buffer 110; first and second peripheral circuits 120 and 130; a variable delay line 140; a phase detector 150; and a compensation delay 160. In addition, the semiconductor memory device has a data output path 200 for outputting data.
An external clock EXT_CLK is applied to the clock buffer 110. The signal responsively produced by the clock buffer 110 is applied to the first peripheral circuit 120 that produces an output with an adjusted level with respect to the external clock EXT_CLK. The variable delay line 140 introduces a variable delay according to a control signal CS generated by the phase detector 150. The delayed clock signal from the variable delay line 140 is applied to the second peripheral circuit 130, which generates an internal clock IN_CLK.
The internal clock IN_CLK is input to the data output path 200, which is a circuit formed of a driver and latch element for outputting the data. The data output path 200 locks the data output from a memory cell to the internal clock IN_CLK and outputs the data to outside through a data pin. The internal clock IN_CLK is fed back to the phase detector 150 via the compensation delay 160 to allow precise locking to the external clock EXT_CLK, so that a feedback loop is formed. The phase detector 150 compares the phases of the external clock EXT_CLK and a feedback clock FB_CLK, to precisely lock the DLL 100.
Accordingly, it is most preferable that the delay times of the data output path 200 and compensation delay 160 are substantially the same, such that the phases of the external clock EXT_CLK and output data DQ are substantially equal. Ideally, the DLL maintains a uniform locking state regardless of changes in temperature and voltage and is insensitive to noise in the external clock EXT_CLK and internal power supply.
FIGS. 2A through 2D illustrate the operation of the typical DLL 100 shown in FIG. 1 while varying the internal power supply of the semiconductor memory device. Dotted lines shown in FIGS. 2A through 2D illustrate the phases at which the phases of the external clock EXT_CLK and output data DQ are substantially identical, and solid lines illustrate the phases at which the phases of the external clock EXT_CLK and output data DQ are substantially different.
FIG. 2A illustrates a case where the variation Δ of delay in the data output path 200 is smaller than the variation Δ′ of delay in the compensation delay 160, showing a momentary response to a reduction in power supply voltage. When the power supply level decreases, jitter having a magnitude of Δ is generated. After a plurality of clock cycles, the DLL 100 is re-locked, and the jitter varies by Δ′ as the power supply level is restored. The locking operation is completed after several more clock cycles. Consequently, jitter having a variation of Δ+Δ′ is generated while the power supply decreases and then is restored.
FIG. 2B illustrates a case where the variation Δ and Δ′ of delays in the data output path 200 and compensation delay 160 are the same, showing a response to a momentary reduction in power supply level. In this case, jitter having a variation of Δ+Δ′, namely 2Δ, is generated, which is less than the jitter shown in FIG. 2A.
FIG. 2C illustrates a case where the variation Δ of delay in the data output path 200 is greater than the variation Δ′ of delay in the compensation delay 160, showing a response to a momentary reduction in power supply level. In this case, jitter having a variation of Δ+Δ′ is generated, which is less than the jitter shown in FIGS. 2A and 2B.
FIG. 2D illustrates a case where the variation Δ′ of delay in the compensation delay 160 is substantially zero. In this case, jitter having a magnitude of Δ is generated as power level first falls and then is restored. This is the least jitter of the cases shown in FIGS. 2A through 2D. In order to minimize performance loss caused by noise in the internal power supply, it is desirable that the variation of the delay in the compensation delay 160 by noise in the power supply minimized, as in FIG. 2D.
FIG. 3 is a block diagram illustrating a conventional semiconductor memory device having a conventional DLL. Referring to FIG. 3, the DLL includes: a clock buffer 310; a variable delay line 340; first and second peripheral circuits 320 and 330; a phase detector 350; and a compensation delay 360. In addition, the DLL further includes a data output path 200 for outputting data.
The variable delay line 340 receives power supply voltage Vdd_dll/Vss_dll through a separate power pin (not shown) and/or a pad 380, in order to reject noise from other peripheral circuits. Other peripheral circuitry 300 receives power Vdd/Vss through a peripheral circuitry power pad 370. Typically, as the number of output pins connected to the output data path 200 increases, power dissipation is greatly increased, causing large power loss and noise. In addition, the noise generated by the data output path 200 can flow into the compensation delay 360 and the clock buffer 310, which uses the same power supply path as the data output path 200. This can cause jitter. It is desirable that power loss and noise generated in the data output path 200 be prevented from significantly affecting the peripheral circuitry of the DLL.